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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - ATOMIC_OP_NEEDS_MEMORY_BARRIER configure check shouldn't be false for ARM"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=90302">90302</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>ATOMIC_OP_NEEDS_MEMORY_BARRIER configure check shouldn't be false for ARM
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>cairo
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>unspecified
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>Other
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>All
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>normal
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>medium
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>general
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>chris@chris-wilson.co.uk
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>froydnj@gmail.com
          </td>
        </tr>

        <tr>
          <th>QA Contact</th>
          <td>cairo-bugs@cairographics.org
          </td>
        </tr></table>
      <p>
        <div>
        <pre>ATOMIC_OP_NEEDS_MEMORY_BARRIER, set by configure:

<a href="http://cgit.freedesktop.org/cairo/tree/build/aclocal.cairo.m4#n203">http://cgit.freedesktop.org/cairo/tree/build/aclocal.cairo.m4#n203</a>

determines whether "atomic" loads need memory barriers prior to the load
itself.  I assume this was put in for performance reasons.

>From the above link, I can see that it's defined to false for x86/x86-64, which
makes sense.  What seems suspicious is that it's also defined to false for ARM,
which has much weaker memory ordering guarantees than x86 by default.</pre>
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