[cairo] [PATCH] SSE2 support for pixman (v2)
andrelrt at gmail.com
Mon Mar 17 11:19:24 PDT 2008
On Mon, Mar 17, 2008 at 12:16 PM, Rodrigo Kumpera <kumpera at gmail.com> wrote:
> It's not that strange if you think from the memory fetching perpective. Both
> the mmx code of the sse code will do the same amount of main memory fetches
> as the cache line is 32 byte wide (or is 64?). The same can be said about
> memory writes, as the same number of bus operations will be done. Since main
> memory operations are in the other of many dozen of cicles, the mmx/sse
> transformation code will basically be noise in the pipeline.
In this case, the problem is to calibrate the prefetch to load memory
to cache as soon as possible to avoid waits for memory reads. Perhaps
we can fetch 64-128 bytes ahead to fill two or three cache lines (the
cache line is 64 byte wide), so the memory reads will be cheaper.
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