[cairo] [patch] gl: set tex_with in cairo_gl_gradient_t instead in cairo_entry.size

Henry (Yu) Song - SISA hsong at sisa.samsung.com
Mon Nov 5 17:34:25 PST 2012


Hi, Chris

I am not sure why cache_entry.size has to be the tex_width.  It seems that tex_width has no relation with cache_entry.size.  In my patch, the cache_entry.size is set at 4, which allows 1024 gradient cached. 

if CAIRO_GL_GRADIENT_CACHE_SIZE = 16384, and let's assume each tex_with is about 64, that is only 256 gradient cache.


The gradient cache should not be limited by system memory, it should, I think, be limited by the GPU memory, because each texture is 1 pixel height, and even, in worst case, each tex_width is 1024, 1024 gradient cache is 4 M (1024x1024x4 (RGBA)) bytes.  - that should be OK, I think

Please comments

Thanks

________________________________________
From: cairo-bounces+henry.song=samsung.com at cairographics.org [cairo-bounces+henry.song=samsung.com at cairographics.org] on behalf of Chris Wilson [chris at chris-wilson.co.uk]
Sent: Monday, November 05, 2012 1:39 PM
To: Henry (Yu) Song - SISA; cairo at cairographics.org
Subject: Re: [cairo] [patch] gl: set tex_with in cairo_gl_gradient_t instead    in cairo_entry.size

On Mon, 5 Nov 2012 21:28:31 +0000, "Henry (Yu) Song - SISA" <hsong at sisa.samsung.com> wrote:
> From 18e714f260f18e6ae13979a289b6f7892d7f82c2 Mon Sep 17 00:00:00 2001
> From: Henry Song <henry.song at samsung.com>
> Date: Mon, 5 Nov 2012 13:16:18 -0800
> Subject: [PATCH] gl: add tex_width in cairo_gl_gradient_t structure, there is
>  no need to set cache_entry.size to be tex_width, this makes
>  it unlikely overflows gradient cache

The idea is that the gradient cache tries to only keep a certain amount
of texture memory cached. It sounds like that limit is too low --
indeed, it is set at 4096 which is only 16k, or roughly 4 gradients.
That would be better with

#define CAIRO_GL_GRADIENT_CACHE_SIZE 16384

judging by desktop usage, and you probably have a better idea for your
use cases.
-Chris

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Chris Wilson, Intel Open Source Technology Centre
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