[cairo] [PATCH 06/71] drm: use typedefs and defines from drm headers instead of redundant own definitions
Bryce Harrington
bryce at osg.samsung.com
Mon Apr 24 22:54:50 UTC 2017
On Mon, Apr 17, 2017 at 06:56:45PM +0200, Enrico Weigelt, metux IT consult wrote:
> These typedefs and defines are part of the libdrm API and therefore should
> be taken from there, instead of own redundant declarations.
>
> Signed-off-by: Enrico Weigelt, metux IT consult <enrico.weigelt at gr13.net>
Reviewed-by: Bryce Harrington <bryce at osg.samsung.com>
Pushed:
To ssh://git.freedesktop.org/git/cairo
72c600a..f7e686c master -> master
> ---
> src/Makefile.sources | 1 -
> src/drm/cairo-drm-bo.c | 33 +--
> src/drm/cairo-drm-i915-surface.c | 1 -
> src/drm/cairo-drm-i965-surface.c | 1 -
> src/drm/cairo-drm-intel-ioctl-private.h | 403 +-------------------------------
> src/drm/cairo-drm-intel.c | 4 +-
> src/drm/cairo-drm-ioctl-private.h | 12 -
> src/drm/cairo-drm-radeon-private.h | 4 -
> src/drm/cairo-drm-radeon-surface.c | 4 +
> src/drm/cairo-drm-radeon.c | 123 +---------
> 10 files changed, 11 insertions(+), 575 deletions(-)
> delete mode 100644 src/drm/cairo-drm-ioctl-private.h
>
> diff --git a/src/Makefile.sources b/src/Makefile.sources
> index b368f2774..b1e3eb13e 100644
> --- a/src/Makefile.sources
> +++ b/src/Makefile.sources
> @@ -416,7 +416,6 @@ cairo_directfb_sources = cairo-directfb-surface.c
>
> cairo_drm_headers = cairo-drm.h
> cairo_drm_private = drm/cairo-drm-private.h \
> - drm/cairo-drm-ioctl-private.h \
> drm/cairo-drm-intel-private.h \
> drm/cairo-drm-intel-brw-defines.h \
> drm/cairo-drm-intel-brw-structs.h \
> diff --git a/src/drm/cairo-drm-bo.c b/src/drm/cairo-drm-bo.c
> index a5b59f2c9..c82f9331d 100644
> --- a/src/drm/cairo-drm-bo.c
> +++ b/src/drm/cairo-drm-bo.c
> @@ -28,46 +28,15 @@
> */
>
> #include "cairoint.h"
> -
> #include "cairo-drm-private.h"
> -#include "cairo-drm-ioctl-private.h"
> -
> #include "cairo-error-private.h"
>
> #include <sys/ioctl.h>
> #include <errno.h>
> +#include <libdrm/drm.h>
>
> #define ERR_DEBUG(x) x
>
> -struct drm_gem_close {
> - /** Handle of the object to be closed. */
> - uint32_t handle;
> - uint32_t pad;
> -};
> -
> -struct drm_gem_flink {
> - /** Handle for the object being named */
> - uint32_t handle;
> -
> - /** Returned global name */
> - uint32_t name;
> -};
> -
> -struct drm_gem_open {
> - /** Name of object being opened */
> - uint32_t name;
> -
> - /** Returned handle for the object */
> - uint32_t handle;
> -
> - /** Returned size of the object */
> - uint64_t size;
> -};
> -
> -#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
> -#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
> -#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
> -
> cairo_status_t
> _cairo_drm_bo_open_for_name (const cairo_drm_device_t *dev,
> cairo_drm_bo_t *bo,
> diff --git a/src/drm/cairo-drm-i915-surface.c b/src/drm/cairo-drm-i915-surface.c
> index 39b42cd86..cdbf258c2 100644
> --- a/src/drm/cairo-drm-i915-surface.c
> +++ b/src/drm/cairo-drm-i915-surface.c
> @@ -94,7 +94,6 @@
> #include "cairoint.h"
>
> #include "cairo-drm-private.h"
> -#include "cairo-drm-ioctl-private.h"
> #include "cairo-drm-intel-private.h"
> #include "cairo-drm-intel-command-private.h"
> #include "cairo-drm-intel-ioctl-private.h"
> diff --git a/src/drm/cairo-drm-i965-surface.c b/src/drm/cairo-drm-i965-surface.c
> index ec7b5954c..04050ef9c 100644
> --- a/src/drm/cairo-drm-i965-surface.c
> +++ b/src/drm/cairo-drm-i965-surface.c
> @@ -48,7 +48,6 @@
> #include "cairoint.h"
>
> #include "cairo-drm-private.h"
> -#include "cairo-drm-ioctl-private.h"
> #include "cairo-drm-intel-private.h"
> #include "cairo-drm-intel-command-private.h"
> #include "cairo-drm-intel-ioctl-private.h"
> diff --git a/src/drm/cairo-drm-intel-ioctl-private.h b/src/drm/cairo-drm-intel-ioctl-private.h
> index 004d3bfd7..6853304d2 100644
> --- a/src/drm/cairo-drm-intel-ioctl-private.h
> +++ b/src/drm/cairo-drm-intel-ioctl-private.h
> @@ -30,412 +30,15 @@
> #ifndef CAIRO_DRM_INTEL_IOCTL_PRIVATE_H
> #define CAIRO_DRM_INTEL_IOCTL_PRIVATE_H
>
> -#include "cairo-drm-intel-command-private.h"
> -
> -#define I915_PARAM_IRQ_ACTIVE 1
> -#define I915_PARAM_ALLOW_BATCHBUFFER 2
> -#define I915_PARAM_LAST_DISPATCH 3
> -#define I915_PARAM_CHIPSET_ID 4
> -#define I915_PARAM_HAS_GEM 5
> -#define I915_PARAM_NUM_FENCES_AVAIL 6
> -#define I915_PARAM_HAS_OVERLAY 7
> -#define I915_PARAM_HAS_PAGEFLIPPING 8
> -#define I915_PARAM_HAS_EXECBUF2 9
> -
> -struct intel_getparam {
> - int param;
> - int *value;
> -};
> -
> -
> -/* @{
> - * Intel memory domains
> - *
> - * Most of these just align with the various caches in
> - * the system and are used to flush and invalidate as
> - * objects end up cached in different domains.
> - */
> -/* CPU cache */
> -#define I915_GEM_DOMAIN_CPU 0x00000001
> -/* Render cache, used by 2D and 3D drawing */
> -#define I915_GEM_DOMAIN_RENDER 0x00000002
> -/* Sampler cache, used by texture engine */
> -#define I915_GEM_DOMAIN_SAMPLER 0x00000004
> -/* Command queue, used to load batch buffers */
> -#define I915_GEM_DOMAIN_COMMAND 0x00000008
> -/* Instruction cache, used by shader programs */
> -#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
> -/* Vertex address cache */
> -#define I915_GEM_DOMAIN_VERTEX 0x00000020
> -/* GTT domain - aperture and scanout */
> -#define I915_GEM_DOMAIN_GTT 0x00000040
> -/* @} */
> -
> -#define I915_TILING_NONE 0
> -#define I915_TILING_X 1
> -#define I915_TILING_Y 2
> -
> -#define I915_BIT_6_SWIZZLE_NONE 0
> -#define I915_BIT_6_SWIZZLE_9 1
> -#define I915_BIT_6_SWIZZLE_9_10 2
> -#define I915_BIT_6_SWIZZLE_9_11 3
> -#define I915_BIT_6_SWIZZLE_9_10_11 4
> -
> -#define DRM_I915_GEM_EXECBUFFER 0x14
> -#define DRM_I915_GEM_BUSY 0x17
> -#define DRM_I915_GEM_THROTTLE 0x18
> -#define DRM_I915_GEM_CREATE 0x1b
> -#define DRM_I915_GEM_PREAD 0x1c
> -#define DRM_I915_GEM_PWRITE 0x1d
> -#define DRM_I915_GEM_MMAP 0x1e
> -#define DRM_I915_GEM_SET_DOMAIN 0x1f
> -#define DRM_I915_GEM_SET_TILING 0x21
> -#define DRM_I915_GEM_GET_TILING 0x22
> -#define DRM_I915_GEM_GET_APERTURE 0x23
> -#define DRM_I915_GEM_MMAP_GTT 0x24
> -
> -struct drm_i915_gem_create {
> - /*
> - * Requested size for the object.
> - *
> - * The (page-aligned) allocated size for the object will be returned.
> - */
> - uint64_t size;
> - /*
> - * Returned handle for the object.
> - *
> - * Object handles are nonzero.
> - */
> - uint32_t handle;
> - uint32_t pad;
> -};
> -
> -struct drm_i915_gem_pread {
> - /* Handle for the object being read. */
> - uint32_t handle;
> - uint32_t pad;
> - /* Offset into the object to read from */
> - uint64_t offset;
> - /* Length of data to read */
> - uint64_t size;
> - /*
> - * Pointer to write the data into.
> - *
> - * This is a fixed-size type for 32/64 compatibility.
> - */
> - uint64_t data_ptr;
> -};
> -
> -struct drm_i915_gem_pwrite {
> - /* Handle for the object being written to. */
> - uint32_t handle;
> - uint32_t pad;
> - /* Offset into the object to write to */
> - uint64_t offset;
> - /* Length of data to write */
> - uint64_t size;
> - /*
> - * Pointer to read the data from.
> - *
> - * This is a fixed-size type for 32/64 compatibility.
> - */
> - uint64_t data_ptr;
> -};
> -
> -struct drm_i915_gem_mmap {
> - /* Handle for the object being mapped. */
> - uint32_t handle;
> - uint32_t pad;
> - /* Offset in the object to map. */
> - uint64_t offset;
> - /*
> - * Length of data to map.
> - *
> - * The value will be page-aligned.
> - */
> - uint64_t size;
> - /*
> - * Returned pointer the data was mapped at.
> - *
> - * This is a fixed-size type for 32/64 compatibility.
> - */
> - uint64_t addr_ptr;
> -};
> -
> -struct drm_i915_gem_mmap_gtt {
> - /* Handle for the object being mapped. */
> - uint32_t handle;
> - uint32_t pad;
> - /*
> - * Fake offset to use for subsequent mmap call
> - *
> - * This is a fixed-size type for 32/64 compatibility.
> - */
> - uint64_t offset;
> -};
> -
> -struct drm_i915_gem_set_domain {
> - /* Handle for the object */
> - uint32_t handle;
> -
> - /* New read domains */
> - uint32_t read_domains;
> -
> - /* New write domain */
> - uint32_t write_domain;
> -};
> -
> -struct drm_i915_gem_relocation_entry {
> - /*
> - * Handle of the buffer being pointed to by this relocation entry.
> - *
> - * It's appealing to make this be an index into the mm_validate_entry
> - * list to refer to the buffer, but this allows the driver to create
> - * a relocation list for state buffers and not re-write it per
> - * exec using the buffer.
> - */
> - uint32_t target_handle;
> -
> - /*
> - * Value to be added to the offset of the target buffer to make up
> - * the relocation entry.
> - */
> - uint32_t delta;
> -
> - /* Offset in the buffer the relocation entry will be written into */
> - uint64_t offset;
> -
> - /*
> - * Offset value of the target buffer that the relocation entry was last
> - * written as.
> - *
> - * If the buffer has the same offset as last time, we can skip syncing
> - * and writing the relocation. This value is written back out by
> - * the execbuffer ioctl when the relocation is written.
> - */
> - uint64_t presumed_offset;
> -
> - /*
> - * Target memory domains read by this operation.
> - */
> - uint32_t read_domains;
> -
> - /*
> - * Target memory domains written by this operation.
> - *
> - * Note that only one domain may be written by the whole
> - * execbuffer operation, so that where there are conflicts,
> - * the application will get -EINVAL back.
> - */
> - uint32_t write_domain;
> -};
> -
> -struct drm_i915_gem_exec_object {
> - /*
> - * User's handle for a buffer to be bound into the GTT for this
> - * operation.
> - */
> - uint32_t handle;
> +#include <drm/i915_drm.h>
>
> - /* Number of relocations to be performed on this buffer */
> - uint32_t relocation_count;
> - /*
> - * Pointer to array of struct drm_i915_gem_relocation_entry containing
> - * the relocations to be performed in this buffer.
> - */
> - uint64_t relocs_ptr;
> -
> - /* Required alignment in graphics aperture */
> - uint64_t alignment;
> -
> - /*
> - * Returned value of the updated offset of the object, for future
> - * presumed_offset writes.
> - */
> - uint64_t offset;
> -};
> -
> -struct drm_i915_gem_execbuffer {
> - /*
> - * List of buffers to be validated with their relocations to be
> - * performend on them.
> - *
> - * This is a pointer to an array of struct drm_i915_gem_validate_entry.
> - *
> - * These buffers must be listed in an order such that all relocations
> - * a buffer is performing refer to buffers that have already appeared
> - * in the validate list.
> - */
> - uint64_t buffers_ptr;
> - uint32_t buffer_count;
> -
> - /* Offset in the batchbuffer to start execution from. */
> - uint32_t batch_start_offset;
> - /* Bytes used in batchbuffer from batch_start_offset */
> - uint32_t batch_len;
> - uint32_t DR1;
> - uint32_t DR4;
> - uint32_t num_cliprects;
> - /* This is a struct drm_clip_rect *cliprects */
> - uint64_t cliprects_ptr;
> -};
> -
> -struct drm_i915_gem_busy {
> - /* Handle of the buffer to check for busy */
> - uint32_t handle;
> -
> - /* Return busy status (1 if busy, 0 if idle) */
> - uint32_t busy;
> -};
> -
> -struct drm_i915_gem_set_tiling {
> - /* Handle of the buffer to have its tiling state updated */
> - uint32_t handle;
> -
> - /*
> - * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
> - * I915_TILING_Y).
> - *
> - * This value is to be set on request, and will be updated by the
> - * kernel on successful return with the actual chosen tiling layout.
> - *
> - * The tiling mode may be demoted to I915_TILING_NONE when the system
> - * has bit 6 swizzling that can't be managed correctly by GEM.
> - *
> - * Buffer contents become undefined when changing tiling_mode.
> - */
> - uint32_t tiling_mode;
> -
> - /*
> - * Stride in bytes for the object when in I915_TILING_X or
> - * I915_TILING_Y.
> - */
> - uint32_t stride;
> -
> - /*
> - * Returned address bit 6 swizzling required for CPU access through
> - * mmap mapping.
> - */
> - uint32_t swizzle_mode;
> -};
> -
> -struct drm_i915_gem_get_tiling {
> - /* Handle of the buffer to get tiling state for. */
> - uint32_t handle;
> -
> - /*
> - * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
> - * I915_TILING_Y).
> - */
> - uint32_t tiling_mode;
> -
> - /*
> - * Returned address bit 6 swizzling required for CPU access through
> - * mmap mapping.
> - */
> - uint32_t swizzle_mode;
> -};
> -
> -struct drm_i915_gem_get_aperture {
> - /* Total size of the aperture used by i915_gem_execbuffer, in bytes */
> - uint64_t aper_size;
> -
> - /*
> - * Available space in the aperture used by i915_gem_execbuffer, in
> - * bytes
> - */
> - uint64_t aper_available_size;
> -};
> -
> -#define DRM_I915_GETPARAM 0x06
> -
> -#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, struct intel_getparam)
> -#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
> -#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
> -#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
> -#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> -#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> -#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> -#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> -#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
> -#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
> -#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
> -#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
> -#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
> -
> -#define I915_MADV_WILLNEED 0
> -#define I915_MADV_DONTNEED 1
> -
> -struct drm_i915_gem_madvise {
> - uint32_t handle;
> - uint32_t madv;
> - uint32_t retained;
> -};
> -#define DRM_I915_GEM_MADVISE 0x26
> -#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
> -
> -
> -/* XXX execbuffer2 */
> -struct drm_i915_gem_exec_object2 {
> - /*
> - * User's handle for a buffer to be bound into the GTT for this
> - * operation.
> - */
> - uint32_t handle;
> -
> - /* Number of relocations to be performed on this buffer */
> - uint32_t relocation_count;
> - /*
> - * Pointer to array of struct drm_i915_gem_relocation_entry containing
> - * the relocations to be performed in this buffer.
> - */
> - uint64_t relocs_ptr;
> -
> - /* Required alignment in graphics aperture */
> - uint64_t alignment;
> -
> - /*
> - * Returned value of the updated offset of the object, for future
> - * presumed_offset writes.
> - */
> - uint64_t offset;
> -
> -#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
> - uint64_t flags;
> - uint64_t rsvd1;
> - uint64_t rsvd2;
> -};
> -
> -struct drm_i915_gem_execbuffer2 {
> - /*
> - * List of gem_exec_object2 structs
> - */
> - uint64_t buffers_ptr;
> - uint32_t buffer_count;
> -
> - /* Offset in the batchbuffer to start execution from. */
> - uint32_t batch_start_offset;
> - /* Bytes used in batchbuffer from batch_start_offset */
> - uint32_t batch_len;
> - uint32_t DR1;
> - uint32_t DR4;
> - uint32_t num_cliprects;
> - /* This is a struct drm_clip_rect *cliprects */
> - uint64_t cliprects_ptr;
> - uint64_t flags;
> - uint64_t rsvd1;
> - uint64_t rsvd2;
> -};
> -
> -#define I915_GEM_3D_PIPELINE 0x1
> -#define I915_GEM_MEDIA_PIPELINE 0x2
> -#define DRM_I915_GEM_EXECBUFFER2 0x29
> -#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
> +#include "cairo-drm-intel-command-private.h"
>
> struct drm_i915_gem_real_size {
> uint32_t handle;
> uint64_t size;
> };
> +
> #define DRM_I915_GEM_REAL_SIZE 0x2a
> #define DRM_IOCTL_I915_GEM_REAL_SIZE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_REAL_SIZE, struct drm_i915_gem_real_size)
>
> diff --git a/src/drm/cairo-drm-intel.c b/src/drm/cairo-drm-intel.c
> index 8bc4ad8be..b5459d90e 100644
> --- a/src/drm/cairo-drm-intel.c
> +++ b/src/drm/cairo-drm-intel.c
> @@ -30,7 +30,6 @@
> #include "cairoint.h"
>
> #include "cairo-drm-private.h"
> -#include "cairo-drm-ioctl-private.h"
> #include "cairo-drm-intel-private.h"
> #include "cairo-drm-intel-ioctl-private.h"
>
> @@ -42,6 +41,7 @@
> #include <sys/ioctl.h>
> #include <sys/mman.h>
> #include <errno.h>
> +#include <drm/i915_drm.h>
>
> #define GLYPH_CACHE_WIDTH 1024
> #define GLYPH_CACHE_HEIGHT 1024
> @@ -54,7 +54,7 @@
> int
> intel_get (int fd, int param)
> {
> - struct intel_getparam gp;
> + struct drm_i915_getparam gp;
> int value;
>
> gp.param = param;
> diff --git a/src/drm/cairo-drm-ioctl-private.h b/src/drm/cairo-drm-ioctl-private.h
> deleted file mode 100644
> index 4294de2d5..000000000
> --- a/src/drm/cairo-drm-ioctl-private.h
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -#ifndef CAIRO_DRM_IOCTL_PRIVATE_H
> -#define CAIRO_DRM_IOCTL_PRIVATE_H
> -
> -#define DRM_IOCTL_BASE 'd'
> -#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
> -#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
> -#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
> -#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
> -
> -#define DRM_COMMAND_BASE 0x40
> -
> -#endif /* CAIRO_DRM_IOCTL_PRIVATE_H */
> diff --git a/src/drm/cairo-drm-radeon-private.h b/src/drm/cairo-drm-radeon-private.h
> index 546126c6f..076852835 100644
> --- a/src/drm/cairo-drm-radeon-private.h
> +++ b/src/drm/cairo-drm-radeon-private.h
> @@ -35,10 +35,6 @@
> #include "cairo-drm-private.h"
> #include "cairo-freelist-private.h"
>
> -#define RADEON_GEM_DOMAIN_CPU 0x1
> -#define RADEON_GEM_DOMAIN_GTT 0x2
> -#define RADEON_GEM_DOMAIN_VRAM 0x4
> -
> typedef struct _radeon_bo {
> cairo_drm_bo_t base;
>
> diff --git a/src/drm/cairo-drm-radeon-surface.c b/src/drm/cairo-drm-radeon-surface.c
> index 17f9abc14..528aab77c 100644
> --- a/src/drm/cairo-drm-radeon-surface.c
> +++ b/src/drm/cairo-drm-radeon-surface.c
> @@ -27,6 +27,10 @@
> *
> */
>
> +#include <stddef.h>
> +#include <inttypes.h> /* workaround for broken <drm/radeon_drm.h> */
> +#include <drm/radeon_drm.h>
> +
> #include "cairoint.h"
>
> #include "cairo-drm-private.h"
> diff --git a/src/drm/cairo-drm-radeon.c b/src/drm/cairo-drm-radeon.c
> index 3f00a4960..8bc91bfe0 100644
> --- a/src/drm/cairo-drm-radeon.c
> +++ b/src/drm/cairo-drm-radeon.c
> @@ -31,7 +31,6 @@
>
> #include "cairo-drm-private.h"
> #include "cairo-drm-radeon-private.h"
> -#include "cairo-drm-ioctl-private.h"
>
> #include "cairo-error-private.h"
> #include "cairo-image-surface-private.h"
> @@ -39,127 +38,7 @@
> #include <sys/ioctl.h>
> #include <sys/mman.h>
> #include <errno.h>
> -
> -#define DRM_RADEON_GEM_INFO 0x1c
> -#define DRM_RADEON_GEM_CREATE 0x1d
> -#define DRM_RADEON_GEM_MMAP 0x1e
> -#define DRM_RADEON_GEM_PREAD 0x21
> -#define DRM_RADEON_GEM_PWRITE 0x22
> -#define DRM_RADEON_GEM_SET_DOMAIN 0x23
> -#define DRM_RADEON_GEM_WAIT_IDLE 0x24
> -#define DRM_RADEON_CS 0x26
> -#define DRM_RADEON_INFO 0x27
> -
> -#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
> -#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
> -#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
> -#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
> -#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
> -#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
> -#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
> -//#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
> -
> -struct drm_radeon_gem_info {
> - uint64_t gart_size;
> - uint64_t vram_size;
> - uint64_t vram_visible;
> -};
> -
> -#define RADEON_GEM_NO_BACKING_STORE 1
> -
> -struct drm_radeon_gem_create {
> - uint64_t size;
> - uint64_t alignment;
> - uint32_t handle;
> - uint32_t initial_domain;
> - uint32_t flags;
> -};
> -
> -struct drm_radeon_gem_mmap {
> - uint32_t handle;
> - uint32_t pad;
> - uint64_t offset;
> - uint64_t size;
> - uint64_t addr_ptr;
> -};
> -
> -struct drm_radeon_gem_set_domain {
> - uint32_t handle;
> - uint32_t read_domains;
> - uint32_t write_domain;
> -};
> -
> -struct drm_radeon_gem_wait_idle {
> - uint32_t handle;
> - uint32_t pad;
> -};
> -
> -struct drm_radeon_gem_busy {
> - uint32_t handle;
> - uint32_t busy;
> -};
> -
> -struct drm_radeon_gem_pread {
> - /** Handle for the object being read. */
> - uint32_t handle;
> - uint32_t pad;
> - /** Offset into the object to read from */
> - uint64_t offset;
> - /** Length of data to read */
> - uint64_t size;
> - /** Pointer to write the data into. */
> - /* void *, but pointers are not 32/64 compatible */
> - uint64_t data_ptr;
> -};
> -
> -struct drm_radeon_gem_pwrite {
> - /** Handle for the object being written to. */
> - uint32_t handle;
> - uint32_t pad;
> - /** Offset into the object to write to */
> - uint64_t offset;
> - /** Length of data to write */
> - uint64_t size;
> - /** Pointer to read the data from. */
> - /* void *, but pointers are not 32/64 compatible */
> - uint64_t data_ptr;
> -};
> -
> -#define RADEON_CHUNK_ID_RELOCS 0x01
> -#define RADEON_CHUNK_ID_IB 0x02
> -
> -struct drm_radeon_cs_chunk {
> - uint32_t chunk_id;
> - uint32_t length_dw;
> - uint64_t chunk_data;
> -};
> -
> -struct drm_radeon_cs_reloc {
> - uint32_t handle;
> - uint32_t read_domains;
> - uint32_t write_domain;
> - uint32_t flags;
> -};
> -
> -struct drm_radeon_cs {
> - uint32_t num_chunks;
> - uint32_t cs_id;
> - /* this points to uint64_t * which point to cs chunks */
> - uint64_t chunks;
> - /* updates to the limits after this CS ioctl */
> - uint64_t gart_limit;
> - uint64_t vram_limit;
> -};
> -
> -#define RADEON_INFO_DEVICE_ID 0x00
> -#define RADEON_INFO_NUM_GB_PIPES 0x01
> -
> -struct drm_radeon_info {
> - uint32_t request;
> - uint32_t pad;
> - uint64_t value;
> -};
> -
> +#include <drm/radeon_drm.h>
>
> cairo_bool_t
> radeon_info (int fd,
> --
> 2.11.0.rc0.7.gbe5a750
>
> --
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